In order to miniaturize electronic components such as digital cameras and cellular phones and the like, semiconductor packages also need to be miniaturized.
In conventional semiconductor packages, bonding wires for connecting terminals of a semiconductor element and wirings of a semiconductor element mounting substrate together and a space in which the bonding wires can be placed are required. Therefore, the space has to be provided between the semiconductor element and the substrate in the semiconductor package. This interferes with the miniaturization of the semiconductor package.
Examples of a method of miniaturizing the semiconductor package include a method in which a functional surface of the semiconductor substrate included in the semiconductor element is electrically connected to a circuit wiring provided on a surface opposite to the functional surface together via penetrating electrodes formed so as to extend through the semiconductor substrate (see Patent Document 1).
In the method disclosed in Patent Document 1, through-holes are formed through a semiconductor substrate, a build-up layer for producing, for example, a laminated substrate is laminated on the semiconductor substrate so that the through-holes are filled with a constituent material of the build-up layer, and then a new hole is formed through the build-up layer within each through-hole. Thereafter, a conductive layer is formed on an inner surface defining the new hole to provide a conductive material (conductive portion). In this way, the penetrating electrodes are formed.
However, in the case where this method in which the through-holes are filled with the constituent material of build-up layer is used, there is a case that warpage of the semiconductor element increases.
Patent Document 1: Japanese Patent Application Laid-Open No. 2005-216970